There is known a reception circuit which has a phase interpolator that generates a polyphase clock output signal of an arbitrary phase from a polyphase clock input signal based on a phase code and a phase fluctuation circuit that gives a fluctuation to a phase code (see Patent Document 1, for example). A phase detection circuit detects a fluctuation of the polyphase clock output signal in relation to the fluctuation of the phase code. A distortion estimation circuit estimates a phase distortion of the phase interpolator based on a detection result of the phase detection circuit. A correction circuit corrects the phase distortion based on an estimation result of the distortion estimation circuit.
Further, there is known a wave detector which gives a symbol sample synchronized with a baud timing by interpolation from an over-sample series of a PSK signal standardized asynchronously with a time of the baud timing (see Patent Document 2, for example). A zero cross phase is estimated from an output wave of a clock extraction means by a straight line interpolation unit of a phase estimation means, and phase difference data is outputted. A stored value of an approximate interpolation ROM, in which an error amount of straight-line approximation is stored, is added to the phase difference data, and a linear interpolation coefficient ROM is referred to.
[Patent Document 1] Japanese Laid-open Patent Publication No. 2012-54720
[Patent Document 2] Japanese Laid-open Patent Publication No. 11-196142
In Patent Document 1, an analog-digital conversion unit analog-digital converts data in synchronicity with the polyphase clock output signal generated by the phase interpolator. A data judgment circuit performs data judgment to output data of the analog-digital conversion unit. Since a phase distortion of the phase interpolator causes a data judgment error, it is necessary to interpolate the phase distortion of the phase interpolator at a high accuracy.